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connection diagrams 8-pin plastic mini-dip (n) package output voltage swing ?volts p-p load resistance ? 30 0 10 10k 20 10 100 1k v s = ?5v 25 15 5 w 8-pin soic (r) package 1 2 3 4 8 7 6 5 AD795 nc ?n +in ? s nc +v s output nc nc = no connect rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low power, low noise precision fet op amp AD795 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features low power replacement for burr-brown opa-111, opa-121 op amps low noise 2.5 m v p-p max, 0.1 hz to 10 hz 11 nv/ ? hz max at 10 khz 0.6 fa/ ? hz at 1 khz high dc accuracy 250 m v max offset voltage 3 m v/ 8 c max drift 1 pa max input bias current low power: 1.5 ma max supply current available in low cost plastic mini-dip and surface mount (soic) packages applications low noise photodiode preamps ct scanners precision l-to-v converters product description the AD795 is a low noise, precision, fet input operational amplifier. it offers both the low voltage noise and low offset drift of a bipolar input op amp and the very low bias current of a fet-input device. the 10 14 w common-mode impedance insures that input bias current is essentially independent of common-mode voltage and supply voltage variations. the AD795 has both excellent dc performance and a guaran- teed and tested maximum input voltage noise. it features 1 pa maximum input bias current and 250 m v maximum offset volt- age, along with low supply current of 1.5 ma max. 1k 10 1 10 100 10k 1k 100 frequency ?hz voltage noise spectral density ?nv/ ? hz AD795 voltage noise spectral density furthermore, the AD795 features a guaranteed low input noise of 2.5 m v p-p (0.1 hz to 10 hz) and a 11 nv/ ? hz max noise level at 10 khz. the AD795 has a fully specified and tested input offset voltage drift of only 3 m v/ c max. the AD795 is useful for many high input impedance, low noise applications. the AD795j and AD795k are rated over the commercial temperature range of 0 c to +70 c. the AD795 is available in 8-pin plastic mini-dip and 8-pin surface mount (soic) packages. 50 0 5 ? 10 ? 30 20 40 4 3 2 1 0 ? ? ? input offset voltage drift ? m v/ c percentage of units sample size = 570 typical distribution of average input offset voltage drift
rev. a C2C AD795Cspecifications AD795jn/jr AD795k parameter conditions min typ max min typ max units input offset voltage 1 initial offset 100 500 50 250 m v offset t min Ct max 300 1000 100 400 m v vs. temperature 3 10 1 3 m v/ c vs. supply (psrr) 86 110 90 110 db vs. supply (psrr) t min Ct max 84 100 87 100 db input bias current 2 either input v cm = 0 v 1 2/3 1 1 pa either input @ t max =v cm = 0 v 23 23 pa either input v cm = +10 v 1 1 pa offset current v cm = 0 v 0.1 1.0 0.1 0.6 pa offset current @ t max =v cm = 0 v 2 2 pa open-loop gain v o = 10 v r load 3 10 k w 110 120 110 120 db r load 3 10 k w 100 108 100 108 db input voltage noise 0.1 hz to 10 hz 1.0 3.3 1.0 2.5 m v p-p f = 10 hz 20 50 20 40 nv/ ? hz f = 100 hz 12 40 12 30 nv/ ? hz f = 1 khz 11 17 11 15 nv/ ? hz f = 10 khz 9 11 9 11 nv/ ? hz input current noise f = 0.1 hz to 10 hz 13 13 fa p-p f = 1 khz 0.6 0.6 fa/ ? hz frequency response unity gain, small signal g = C1 1.6 1.6 mhz full power response v o = 20 v p-p r load = 2 k w 16 16 khz slow rate, unity gain v out = 20 v p-p r load = 2 k w 11v/ m s settling time 3 to 0.1% 10 v step 10 10 m s to 0.01% 10 v step 11 11 m s overload recovery 4 50% overdrive 2 2 m s total harmonic f = 1 khz distortion r1 3 10 k w v o = 3 v rms C108 C108 db input impedance differential v diff = 1 v 10 12 i 210 12 i 2 w i pf common mode 10 14 i 2.2 10 14 i 2.2 w i pf input voltage range differential 5 20 20 v common-mode voltage 10 11 10 11 v over max operating temperature 10 10 v common-mode rejection ratio v cm = 10 v 90 110 94 110 db t min Ct max 86 100 90 100 db output characteristics voltage r load 3 2 k w v s C4 v s C2.5 v s C4 v s C2.5 v t min Ct max v s C4 v s C4 v current v out = 10 v 5 10 5 10 ma short circuit 15 15 ma power supply rated performance 15 15 v operating range 4 18 4 18 v quiescent current 1.3 1.5 1.3 1.5 ma (@ +25 8 c and 6 15 v dc unless otherwise noted)
notes 1 input offset voltage specifications are guaranteed after 5 minutes of operation at t a = +25 c. 2 bias current specifications are guaranteed maximum at either input after 5 minutes of operation at t a = +25 c. for higher temperature, the current doubles every 10 c. 3 gain = C1, r1 = 10 k w . 4 defined as the time required for the amplifiers output to return to normal operation after removal of a 50% overload from the amplifier input. 5 defined as the maximum continuous voltage between the inputs such that neither input exceeds 10 v from ground. all min and max specifications are guaranteed. specifications subject to change without notice. AD795 rev. a C3C absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 (@ t a = +25 c) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mw 8-pin mini-dip package . . . . . . . . . . . . . . . . . . . . 750 mw input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . +v s and Cv s storage temperature range (n, r) . . . . . . . C65 c to +125 c operating temperature range AD795j/k . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to +70 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-pin plastic mini-dip package: q ja = 100 c/watt 8-pin small outline package: q ja = 155 c/watt esd susceptibility esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 volts, which readily accumulate on the human body and on test equipment, can discharge without detection. although the AD795 features proprietary esd pro- tection circuitry, permanent damage may still occur on these devices if they are subjected to high energy electrostatic dis- charges. therefore, proper esd precautions are recommended to avoid any performance degradation or loss of functionality. ordering guide model temperature range package option* AD795jn 0 c to +70 c n-8 AD795kn 0 c to +70 c n-8 AD795jr 0 c to +70 c r-8 *n = plastic mini-dip; r = soic package.
AD795Ctypical characteristics rev. a C4C supply voltage ??olts input common mode range ??olts 20 0 020 15 5 5 10 10 15 r l = 10k +v in ? in w figure 1. common-mode voltage range vs. supply output voltage swing ?volts p-p load resistance ? 30 0 10 10k 20 10 100 1k v s = ?5v 25 15 5 w figure 3. output voltage swing vs. load resistance input bias current ?pa percentage of units 50 0 2 10 0 30 20 40 1.5 1 .5 sample size = 1058 figure 5. typical distribution of input bias current output voltage range ??olts supply voltage ??olts 20 0 020 15 5 5 10 10 15 r l = 10k +v out ? out w figure 2. output voltage range vs. supply voltage 0 20 5 15 10 supply voltage ??olts input bias current ?pa 1.0 0.60 0.70 0.65 0.80 0.75 0.85 0.90 0.95 figure 4. input bias current vs. supply 10 ? 10 ?4 140 10 ?1 10 ?3 ?0 10 ?2 ?0 10 ?0 120 100 80 60 40 20 0 ?0 input bias current ?amps temperature ? c figure 6. input bias current vs. temperature
AD795 rev. a C5C differential input voltage ??olts input bias current ?amperes ? ? ? ? ? ? 0 12 4 ? in +i in 56 3 10 ? 10 ? 10 ? 10 ? 10 ? 10 ? 10 ?0 10 ?1 10 ?2 10 ?3 10 ?4 figure 8. input bias current vs. differential input voltage voltage noise ? m v p-p source resistance w 1k 10 1.0 10 3 10 4 10 9 10 8 10 7 10 6 10 5 noise bandwidth: 0.1 to 10hz 100 figure 10. input voltage noise vs. source resistance frequency ?hz 1k 10 1.0 100 1 10 10m 1m 100k 10k 1k 100 voltage noise (referred to input) ?nv/ ? hz figure 12. input voltage noise spectral density 1.00 0.60 +15 0.70 0.65 ?0 ?5 0.80 0.75 0.85 0.90 0.95 +10 +5 0 ? input bias current ?pa common mode voltage ? volts figure 7. input bias current vs. common-mode voltage ?0 140 ?0 100 120 80 60 40 20 0 ?0 temperature ? c voltage noise ?nv/ ? hz 15 12.5 10 7.5 5 100 10 1.0 0.1 0.01 current noise ?fa/ ? hz voltage noise current noise f = 1khz figure 9. voltage and current noise spectral density vs. temperature 0.1 to 10hz input voltage noise p-p ? m v percentage of units 50 0 3 10 0 30 20 40 2 1 sample size = 344 f = 0.1 to 10hz figure 11. typical distribution of input voltage noise
AD795Ctypical characteristics rev. a C6C 10 ?0 11 ? ? 4 ? 3 2 ? 0 4 6 8 10 9 8 7 6 5 setting time ?? output swing from 0 to ? 0.1% 0.01% 0.1% 0.01% aa aa error figure 14. output swing and error vs. settling time frequency ?hz power supply rejection db 120 60 0 1 10 10m 1m 100k 10k 1k 100 40 20 80 100 ?srr +psrr figure 16. power supply rejection vs. frequency 120 ?0 10m 40 0 100 20 10 100 60 80 1m 100k 10k 1k frequency ?hz open-loop gain ?db phase margin ?degrees gain phase 120 ?0 40 0 20 100 60 80 figure 18. open-loop gain & phase margin vs. frequency 30 5 140 20 10 ?0 15 ?0 25 120 100 80 60 40 20 0 ?0 temperature ? c short circuit current ?ma + output current ?output current figure 13. short circuit current limit vs. temperature 1000 0 15 300 100 ?0 200 ?5 600 400 500 700 800 900 10 5 0 ? input common mode voltage ?volts absolute input error voltage ? m v figure 15. absolute input error voltage vs. input common-mode voltage frequency ?hz common mode rejection ?db 120 60 0 1 10 10m 1m 100k 10k 1k 100 40 20 80 100 figure 17. common-mode rejection vs. frequency
AD795 rev. a C7C closed-loop output impedance w frequency ?hz 1000 10 0.1 10k 10m 1m 100k 1k 100 1.0 figure 20. closed-loop output impedance vs. frequency quiescent supply current ?ma 20 5 015 10 supply voltage ?volts 2.0 1.0 0.5 1.5 0 figure 22. quiescent supply current vs. supply voltage drift frequency ?hz output voltage ?volts p-p 30 10 0 10k 100k 1m 20 1k 5 15 25 r l = 10k w figure 19. large signal frequency response frequency ?hz thd ?db 100 1k 100k 10k ?0 ?0 ?20 ?00 ?10 ?0 ?0 v in = 3vrms r l = 10k figure 21. total harmonic distortion vs. frequency input offset voltage ?? percentage of units 50 0 500 ?00 10 ?00 30 20 40 400 300 200 100 0 ?00 ?00 ?00 sample size = 1419 figure 23. typical distribution of input offset voltage
AD795 rev. a C8C 10 90 100 5v 20v 5 m s 0% figure 25. unity gain inverter large signal pulse response 10 90 100 5v 20v 5 m s 0% figure 28. unity gain follower large signal pulse response 7 6 4 3 2 10k w v in ? s 0.1 m f r l 10k w v out 10k w c l 100pf 0.1 m f +v s AD795 figure 24. unity gain inverter 7 6 4 3 2 v in ? s 0.1 m f r l 10k w v out c l 100pf 0.1 m f +v s AD795 figure 27. unity gain follower 10 90 100 10mv 500n s 0% figure 26. unity gain inverter small signal pulse response 10 90 100 20mv 500n s 0% figure 29. unity gain follower small signal pulse response minimizing input current the AD795 is guaranteed to 1 pa max input current with 15 volt supply voltage at room temperature. careful attention to how the amplifier is used will maintain or possibly better this performance. the amplifiers operating temperature should be kept as low as possible. like other jfet input amplifiers, the AD795s input current will double for every 10 c rise in junction temperature (illustrated in figure 6). on-chip power dissipation will raise the device operating temperature, causing an increase in input current. reducing supply voltage to cut power dissipation will reduce the AD795s input current (figure 4). heavy output loads can also increase chip temperature, maintaining a minimum load resistance of 10 k w is recommended.
AD795 rev. a C9C circuit board notes the AD795 is designed for throughhole mounting on pc boards, using either mini-dip or surface mount (soic). maintaining picoampere resolution in those environments requires a lot of care. both the board and the amplifiers package have finite resistance. voltage differences between the input pins and other pins as well as pc board metal traces will cause parasitic currents (figure 30) larger than the AD795s input current unless special precautions are taken. two methods of minimizing parasitic leakages are guarding of the input lines and maintaining adequate insulation resistance. figures 31 and 32 show the recommended guarding schemes for follower and inverted topologies. note that for the mini-dip, the guard trace should be on both sides of the board. on the soic, pin 1 is not connected, and can be safely connected to the guard. the high impedance input trace should be guarded on both edges for its entire length. 6 3 2 AD795 c f v out r f i s + v e i p r p v s c p i p = + v s + c p v s r p dc p dt dv s dt figure 30. sources of parasitic leakage currents 6 3 2 1 2 3 4 8 7 6 5 top view ("n" package) AD795 8 7 6 5 1 2 3 4 bottom view ("n" package) guard traces parallel to both edges of input trace input trace to analog common AD795 c f v out guard r f i s + 1 2 3 4 8 7 6 5 ? s ("r" package) top view note: on the "r" package pins 1, 5 and 8 are open and can be connected to analog common or to the driven guard to reduce leakage. figure 31. guarding schemeClnverter 6 2 3 1 2 3 4 8 7 6 5 AD795 guard traces input trace AD795 v out guard v s + r f r i + connect to junction of r f and r i , or to pin 6 for unity gain. ? s top view figure 32. guard schemeCfollower
AD795 rev. a C10C leakage through the bulk of the circuit board will still occur with the guarding schemes shown in figures 31 and 32. stan- dard g10 type printed circuit board material may not have high enough volume resistivity to hold leakages at the sub- picoampere level particularly under high humidity conditions. one option that eliminates all effects of board resistance is shown in figure 33. the AD795s sensitive input pin (either pin 2 when connected as an inverter, or pin 3 when connected as a follower) is bent up and soldered directly to a teflon* insulated standoff. both the signal input and feedback compo- nent leads must also be insulated from the circuit board by teflon standoffs or low-leakage shielded cable. 1 2 3 4 8 7 6 5 AD795 AD795 teflon insulated standoff input signal lead input pin: pin 2 for inverter or pin 3 for follower pc board figure 33. input pin to insulating standoff contaminants such as solder flux on the boards surface and on the amplifiers package can greatly reduce the insulation resis- tance between the input pin and those traces with supply or signal voltages. both the package and the board must be kept clean and dry. an effective cleaning procedure is to first swab the surface with high grade isopropyl alcohol, then rinse it with deionized water and, finally, bake it at 100 c for 1 hour. poly- propylene and polystyrene capacitors should not be subjected to the 100 c bake as they will be damaged at temperatures greater than 80 c. other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. keeping circuit board components rigid and minimizing vibration will reduce triboelectric and piezoelectric effects. all precision high impedance circuitry requires shielding from electrical noise and interference. for example, a ground plane should be used under all high value (i.e., greater than 1 m w ) feedback resistors. in some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. referring to the equation in figure 30, this coupling can take place in either, or both, of two different formscoupling via time varying fields: dv dt c p or by injection of parasitic currents by changes in capacitance due to mechanical vibration: dcp dt v *teflon is a registered trademark of e.i. du pont co. both proper shielding and rigid mechanical mounting of components help minimize error currents from both of these sources. offset nulling the AD795s input offset voltage can be nulled (mini-dip package only) by using balance pins 1 and 5, as shown in figure 34. nulling the input offset voltage in this fashion will introduce an added input offset voltage drift component of 2.4 m v/ c per millivolt of nulled offset. 1 6 5 4 3 2 AD795 7 +v s v out 100k w ? s + figure 34. standard offset null circuit the circuit in figure 35 can be used when the amplifier is used as an inverter. this method introduces a small voltage in series with the amplifiers positive input terminal. the amplifiers input offset voltage drift with temperature is not affected. however, variation of the power supply voltages will cause offset shifts. 6 3 2 AD795 r i v out r f v i + 499k w 499k w 200 w 0.1 m f 100k w +v s ? s + figure 35. alternate offset null circuit for inverter
AD795 rev. a C11C ac response with high value source and feedback resistance source and feedback resistances greater than 100 k w will magnify the effect of input capacitances (stray and inherent to the AD795) on the ac behavior of the circuit. the effects of common-mode and differential input capacitances should be taken into account since the circuits bandwidth and stability can be adversely affected. in a follower, the source resistance, r s , and input common- mode capacitance, c s (including capacitance due to board and capacitance inherent to the AD795), form a pole that limits circuit bandwidth to 1/2 p r s c s . figure 36 shows the follower pulse response from a 1 m w source resistance with the amplifiers input pin isolated from the board, only the effect of the AD795s input common-mode capacitance is seen. 10 90 100 10mv 5 m s 0% figure 36. follower pulse response from 1 m w source resistance in an inverting configuration, the differential input capacitance forms a pole in the circuits loop transmission. this can create peaking in the ac response and possible instability. a feedback capacitance can be used to stabilize the circuit. the inverter pulse response with r f and r s equal to 1 m w , and the input pin isolated from the board appears in figure 37. figure 38 shows the response of the same circuit with a 1 pf feedback capacitance. typical differential input capacitance for the AD795 is 2 pf. 10 90 100 10mv 5 m s 0% figure 37. inverter pulse response with 1 m w source and feedback resistance 10 90 100 10mv 5 m s 0% figure 38. inverter pulse response with 1 m w source and feedback resistance, 1 pf feedback capacitance overload issues driving the amplifier output beyond its linear region causes some sticking; recovery to normal operation is within 2 m s of the input voltage returning within the linear range. if either input is driven below the negative supply, the amplifiers output will be driven high, causing a phenomenon called phase reversal. normal operation is resumed within 30 m s of the input voltage returning within the linear range. figure 39 shows the AD795s input currents versus differential input voltage. picoamp level input current is maintained for differential voltages up to several hundred millivolts. this behavior is only important if the AD795 is in an open-loop application where substantial differential voltages are produced. ? n +i n 10 ? 10 ? 10 ? 10 ? 10 ? 10 ?0 10 ?1 10 ?2 10 ?3 10 ?4 10 ? ? ? ? ? ? ? 0 1 2 3 4 5 6 differential input voltage ? volts input bias current ?amperes figure 39. input bias current vs. differential input voltage
AD795 rev. a C12C input protection the AD795 safely handles any input voltage within the supply voltage range. some applications may subject the input terminals to voltages beyond the supply voltagesin these cases, the following guidelines should be used to maintain the AD795s functionality and performance. if the inputs are driven more than a 0.5 v below the minus sup- ply, milliamp level currents can be produced through the input terminals. that current should be limited to 10 ma for tran- sient overloads (less than 1 second) and 1 ma for continuous overloads, this can be accomplished with a protection resistor in the input terminal (as shown in figures 40 and 41). the pro- tection resistors johnson noise will add to the amplifiers input voltage noise and impact the frequency response. driving the input terminals above the positive supply will cause the input current to increase and limit at 40 m a. this condition is maintained until 15 volts above the positive supplyany input voltage within this range does not harm the amplifier. input voltage above this range causes destructive breakdown and should be avoided. 6 3 2 source AD795 r f c f r p figure 40. inverter with input current limit 6 2 3 source AD795 r p figure 41. follower with input current limit figure 42 is a schematic of the AD795 as an inverter with an input voltage clamp. bootstrapping the clamp diodes at the inverting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. low leakage diodes (less than 1 pa), such as the fd333s should be used, and should be shielded from light to keep photocurrents from being generated. even with these precautions, the diodes will mea- surably increase the input current and capacitance. in order to achieve the low input bias currents of the AD795, it is not possible to use the same on-chip protection as used in other analog devices op amps. this makes the AD795 sensitive to handling and precautions should be taken to minimize esd exposure whenever possible. 6 3 2 source AD795 r f protect diodes (low leakage) figure 42. input voltage clamp with diodes
AD795 rev. a C13C will typically drop by a factor of two for every 10 c rise in temperature. in the AD795, both the offset voltage and drift are low, this helps minimize these errors. minimizing noise contributions the noise level limits the resolution obtainable from any pre- amplifier. the total output voltage noise divided by the feedback resistance of the op amp defines the minimum detectable signal current. the minimum detectable current divided by the photodiode sensitivity is the minimum detectable light power. sources of noise in a typical preamp are shown in figure 45. the total noise contribution is defined as: v out = ( i n 2 + i f 2 + i s 2 ) rf 1 + s ( cf ) rf ? ? ? ? 2 + ( en 2 ) 1 + rf rd 1 + s ( cd ) rd 1 + s ( cf ) rf ? ? ? ? ? ? ? ? ? 2 photodiode output 10 w 9 50pf i s i s rd cd 10pf cf rf i f i n en figure 45. noise contributions of various sources figure 46, a spectral density versus frequency plot of each sources noise contribution, shows that the bandwidth of the amplifiers input voltage noise contribution is much greater than its signal bandwidth. in addition, capacitance at the summing junction results in a peaking of noise gain in this configura- tion. this effect can be substantial when large photodiodes with large shunt capacitances are used. capacitor cf sets the signal bandwidth and also limits the peak in the noise gain. each sources rms or root-sum-square contribution to noise is ob- tained by integrating the sum of the squares of all the noise sources and then by obtaining the square root of this sum. minimizing the total area under these curves will optimize the preamplifiers overall noise performance. an output filter with a passband close to that of the signal can greatly improve the preamplifiers signal to noise ratio. the photodiode preamplifier shown in figure 45without a bandpass filterhas a total output noise of 50 m v rms. using a 26 hz single pole output filter, the total output noise drops to 23 m v rms, a factor of 2 improvement with no loss in signal bandwidth. 10pf AD795 photodiode guard output 10 w 9 optional 26hz filter filtered output 6 8 3 2 figure 43. the AD795 used as a photodiode preamplifier preamplifier applications the low input current and offset voltage levels of the AD795 together with its low voltage noise make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. in a typical preamp circuit, shown in figure 43, the output of the amplifier is equal to: v out = i d (rf) = rp (p) rf where: i d = photodiode signal current (amps) rp = photodiode sensitivity (amp/watt) rf = the value of the feedback resistor, in ohms. p = light power incident to photodiode surface, in watts. an equivalent model for a photodiode and its dc error sources is shown in figure 44. the amplifiers input current, i b , will contribute an output voltage error which will be proportional to the value of the feedback resistor. the offset voltage error, v os , will cause a dark current error due to the photodiodes finite shunt resistance, rd. the resulting output voltage error, v e , is equal to: v e = ( 1 + rf/rd) v os + rf i b a shunt resistance on the order of 10 9 ohms is typical for a small photodiode. resistance rd is a junction resistance which photodiode output 10pf 10 w 9 i d os v i b rd 50pf cd cf rf figure 44. a photodiode model showing dc error sources
AD795 rev. a C14C frequency ?hz 100 1k 10k 100k 10 1 10nv 100nv 1 m v 10 m v signal bandwidth no filter with filter e n & i s i f i n en output voltage noise ?volts/ ? hz figure 46. voltage noise spectral density of the circuit of figure 45 with and without an output filter photodiode AD795 10pf v out r g 10 w 8 10 k w rf v = i rf (1+ ) out d r i r g r 1.1k w i figure 47. a photodiode preamp employing a t network for added gain using a t network a t network, shown in figure 47, can be used to boost the effective transimpedance of an i-to-v converter, for a given feedback resistor value. however, amplifier noise and offset voltage contributions are also amplified by the t network gain. a low noise, low offset voltage amplifier, such as the AD795, is needed for this type of application. a ph probe buffer amplifier a typical ph probe requires a buffer amplifier to isolate its 10 6 to 10 9 w source resistance from external circuitry. just such an amplifier is shown in figure 48. the low input current of the AD795 allows the voltage error produced by the bias current and electrode resistance to be minimal. the use of guarding, shielding, high insulation resistance standoffs, and other such standard methods used to minimize leakage are all needed to maintain the accuracy of this circuit. the slope of the ph probe transfer function, 50 mv per ph unit at room temperature, has a +3300 ppm/ c temperature coefficient. the buffer of figure 48 provides an output voltage equal to 1 volt/ph unit. temperature compensation is provided by resistor rt which is a special temperature compensation resistor, part number q81, 1 k w , 1%, +3500 ppm/ c, available from tel labs inc. guard AD795 ? s v adjust 100k w os ph probe +v s output 1volt/ph unit 19.6k w rt 1k w +3500ppm/ c 0.1 m f 0.1 m f +15v com ?5v ? s +v s 1 3 2 4 5 6 7 8 figure 48. a ph probe amplifier
AD795 rev. a C15C low noise op amps fast (sr 3 45 v/?) low v n (v n 10 nv/ ? hz @ 1 khz) precision ad op27 op27 ad op37 op37 op227 (dual) op270 (dual) op271 (dual) op470 (quad) op471 (quad) high output current op50 low i n (i n 10 fa/ ? hz @ 1 khz) op61 faster (sr 3 230 v/?) ad5539 ad829 ad840 ad844 ad846 ad848 ad849 ultrafast (sr 3 1000 v/?) ad811 ad844 ad9610 ad9617 ad9618 fast low power low v n ad645 AD795 ad548 ad648 op80 lower v n ad743 electrometer ad711 ad712 (dual) op249 (dual) ad713 (quad) faster ad744 op42 op44 ad746 (dual) faster (sr 3 8 v/?) op282 (dual) op482 (quad) ad745 low power op80 lowest i b 60 fa max ad549 general purpose ad546 fet input ad645 ad743 AD795 fast ad745 op275 ssm2015 ssm2016 ssm2017 ssm2134 ssm2139 audio amplifiers faster low noise op amp selection tree
AD795 rev. a C16C outline dimensions dimensions shown in inches and (mm). plastic mini-dip (n) package 0.011 0.003 (0.28 0.08) 0.30 (7.62) ref 15 0 pin 1 4 5 8 1 0.25 (6.35) 0.31 (7.87) 0.10 (2.54) bsc seating plane 0.035 0.01 (0.89 0.25) 0.18 0.03 (4.57 0.76) 0.033 (0.84) nom 0.018 0.003 (0.46 0.08) 0.125 (3.18) min 0.165 0.01 (4.19 0.25) 0.39 (9.91) max 8-pin soic (r) package 0.019 (0.48) 0.014 (0.36) 0.050 (1.27) bsc 0.102 (2.59) 0.094 (2.39) 0.197 (5.01) 0.189 (4.80) 0.010 (0.25) 0.004 (0.10) 0.098 (0.2482) 0.075 (0.1905) 0.190 (4.82) 0.170 (4.32) 0.030 (0.76) 0.018 (0.46) 10 0 0.090 (2.29) 8 0 0.020 (0.051) x 45 chamf 1 8 5 4 pin 1 0.157 (3.99) 0.150 (3.81) 0.244 (6.20) 0.228 (5.79) 0.150 (3.81) all brand or product names mentioned are trademarks or registered trademarks of their respective holders. c1712C24C10/92 printed in u.s.a.

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